English: Three-bit full adder (add with carry) using five Fredkin gates. The "g" garbage output bit is (p NOR q) if r=0, and (p NAND q) if r=1.

Inputs on the left, including two constants, go through three gates to quickly determine the parity. The 0 and 1 bits swap places for each input bit that is set, resulting in parity bit on the 4th row and inverse of parity on 5th row.

Then the carry row and the inverse parity row swap if the parity bit is set and swap again if one of the p or q input bits are set (it doesn't matter which is used) and the resulting carry output appears on the 3rd row.

The p and q inputs are only used as gate controls, so they appear unchanged in the output.